1. Technology Field
The invention generally relates to a clock adjustment circuit, and in particular, to a digital clock adjustment circuit and a digital to analog converting device using the same.
2. Description of Related Art
Among some digital to analog converting devices, a phase lock loop is usually configured to generate a clock signal, and the clock signal may serve for the modulation or for the sampling of the digital to analog converting process. In some applications, the noise immunity of an all digital phase lock loop is better than that of an analog phase lock loop. The all digital phase lock loop often includes a phase detector, a time to digital converter (TDC), a digital control oscillator, and a divider. To achieve less jitter, the phase detector and/or the digital control oscillator need to have a higher resolution or precision, but that will increase the complexity or the cost of the circuit accordingly. Therefore, it is a topic concerned by those skilled in the art to design a circuit achieving the function of the all digital phase lock loop with lower circuit complexity.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.